DIGITAL ELECTRONICS

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CHAPTER 1: INTRODUCTION       

1) What is Signal?
2) What is Analog Signal?
3) What is Digital Signal?
4) Need of Digital Signal.
5) Introduction to Digital Electronics.
6) Switches and bits.

CHAPTER 2: BOOLEAN ALGEBRA

7) Introduction to Boolean Algebra (Part 1).
8) Introduction to Boolean Algebra (Part 2).
9) Boolean Algebra Examples (Part 1)
10) Boolean Algebra Examples (Part 2)
11) Redundancy Theorem (Boolean Algebra Trick)
12) Sum of Products (Part 1) | SOP Form
13) Sum of Products (Part 2) | SOP Form
14) Product of Sums (Part 1) | POS Form
15) Product of Sums (Part 2) | POS Form
16) SOP and POS Form Examples
17) Minimal to Canonical Form Conversion (Part 1)
18) Minimal to Canonical Form Conversion (Part 2)
19) Examples & Tricks (SOP and POS Forms)
20) Positive and Negative Logic
21) Dual Form
22) Self Dual
23) Complement Meaning and Examples
24) Venn Diagram Examples
25) Switching Circuit (Part 1)
26) Switching Circuit (Part 2)
27) Statement Problem in Boolean Algebra (Part 1)
28) Statement Problem in Boolean Algebra (Part 2)

CHAPTER 3: NUMBER SYSTEM

29) Introduction to Number Systems
30) Binary Number System
31) Decimal to Binary Conversion
32) Decimal to Octal Conversion
33) Decimal to Hexadecimal Conversion.
34) Binary to Decimal Conversion.
35) Octal to Decimal Conversion.
36) Hexadecimal to Decimal Conversion.
37) Octal to Binary & Binary to Octal Conversion
38) Hexadecimal to Binary & Binary to Hexadecimal Conversion
39) Hexadecimal to Octal & Octal to Hexadecimal Conversion
40) Binary Addition.
41) Binary Subtraction.
42) Binary Multiplication.
43) Binary Division.
44) Octal Addition
45) Octal Subtraction
46) Octal Multiplication
47) Hexadecimal Addition
48) Hexadecimal Subtraction
49) Hexadecimal Multiplication
50) r's Compliment.
51) (r-1)'s Compliment.
52) 1's and 2's Complement
53) Shortcut for 2's Complement
54) Data Representation using Signed Magnitude
55) Data Representation using 1's Complement
56) Data Representation using 2's Complement
57) Binary Subtraction using 1's Complement
58) Binary Subtraction using 2's Complement


CHAPTER 4: CODES

59) Classification of Codes
60) Binary Coded Decimal (BCD) Code
61) BCD Addition.
62) 2421 Code.
63) Excess-3 Code (XS-3 Code)
64) Excess-3 Code Addition 
65) Introduction to Gray Code
66) Binary to Gray Code Conversion
67) Gray Code to Binary Conversion
68) What is Parity?
69) Hamming Code | Error Detection Part.
70) Hamming Code | Error Correction Part.


CHAPTER 5: LOGIC GATES

44) Logic Gate Part 1.
45) Logic Gate Part 2.
46) Logic Gate Part 3.
47) Logic Gate Part 4.
48) Logic Gate Part 5.
49) Logic Gate Part 6.
50) NAND as Universal Gate.
51) NOR as Universal Gate.


IES PREVIOUS YEAR QUESTION AND SOLUTION (FOR CH. 1,2,3 & 5)

58) IES Previous Year Solution Part 1.
59) IES Previous Year Solution Part 2.
60) IES Previous Year Solution Part 3.
61) IES Previous Year Solution Part 4.
62) IES Previous Year Solution Part 5. 

CHAPTER 6: KARNAUGH MAP (K' MAP) & IMPLICANTS

63) Karnaugh Map (K' Map) Part 1
64) Karnaugh Map (K' Map) Part 2
65) Karnaugh Map (K' Map) Part 3
66) K' Map and Implicants.
67) 4 Variable Karnaugh Map part 1.
68) 4 Variable Karnaugh Map part 2.
69) 4 Variable Karnaugh Map part 3.
70) Don't Care in K' Map. 
71) K' Map using Max Term Part 1.
72) K' Map using Max Term Part 2.
73) 5 Variable K' Map.

DRDO & ISRO PREVIOUS YEAR QUESTION AND SOLUTION (FOR CH. 6)

74) Previous Year Question and Solutions of DRDO and ISRO Part 1.
75) Previous Year Question and Solutions of DRDO and ISRO Part 2.
76) Previous Year Question and Solutions of DRDO and ISRO Part 3. 
78) 4-bit Even Parity Generator.
79) Seven Segment Display Decoder.
80) Seven Segment Display Decoder (Part 2).
81) Seven Segment Display Decoder (Part 3).


CHAPTER 7: COMBINATIONAL CIRCUITS

84) Comparison between Combinational & Sequential Circuit.
85) Half Adder.
86) Full Adder (Part 1).
87) Full Adder (Part 2).
88) Half Subtractor.
89) Full Subtractor.
90) Shift Add 3 Method | Simple Method for Binary to BCD Conversion.
91) Realizing Half Adder using NAND Gate only.
92) Realizing Half Adder using NOR Gate only.
93) Realizing Full Adder using NAND Gate only.
94) Realizing Half Subtractor using NAND Gate only.
95) Realizing Full Subtractor using NOR Gate only.
96) Carry Lookahead Adder (Part 1) | CLA Generator.
97) Carry Lookahead Adder (Part 2) | CLA Adder.
98) Introduction to Multiplexers | MUX Basic.
99) 4X1 Multiplexer.
100) 8X1 Multiplexer.
101) MUX Tree Basic | 4X1 MUX using 2X1 MUX | Easy Expalnation.
102) Implementing 8X1 MUX using 2X1 MUX.
103) Implementing 8X1 MUX using 4X1 MUX (Special Case).
104) Implementation of Boolean Function using Multiplexers.
105) 1-Bit Full Adder using Multiplexer.
106) Logical Expression from Multiplexers.
107) 2-Bit Comparator.
108) Introduction to Encoders and Decoders.
109) Priority Encoder.
110) Decimal to BCD Encoder.
111) Octal to Binary Encoder.
112) Hexadecimal to Binary Encoder.
113) Full Adder Implementation using Decoder.
114) Practice Problems on Combinational Circuits (Part 1).
115) Practice Problems on Combinational Circuits (Part 2).
116) Practice Problems on Combinational Circuits (Part 3).
117) Practice Problems on Combinational Circuits (Part 4).

CHAPTER 8: SEQUENTIAL CIRCUITS

118) Introduction to Sequential Circuits | Important.
119) SR Latch | NOR and NAND SR Latch.
120) What is Clock?
121) Triggering Methods in Flip Flops.
122) Difference between Latch and Flip Flop.
123) Introduction to SR Flip Flop.
124) Truth Table, Characteristic Table and Excitation Table for SR Flip Flop.
125) Introduction to D Flip Flop.
126) Truth Table, Characteristic Table and Excitation Table for D Flip Flop.
127) Introduction to JK Flip flop.
128) Truth Table, Characteristic Table and Excitation Table for JK Flip Flop.
129) Race Around Condition or Racing in JK Flip Flop.
130) Master Slave JK Flip Flop.
131) Introduction to T  Flip Flop.
132) Truth Table, Characteristic Table and Excitation Table for T Flip Flop.
133) 5 Steps for Flip Flop Conversions | JK to D Flip Flop Conversion.
134) T Flip Flop to D Flip Flop Conversion.
135) SR Flip Flop to JK Flip Flop Conversion.
136) SR Flip Flop to T Flip Flop Conversion.
137) Preset and Clear Inputs in  Flip Flop.
138) How to Get Edge Triggering | Simulation using Multisim.
139) Difference Between Synchronous and Asynchronous Sequential Circuits.
140) Introduction to Counters | Important.
141) Introduction to State Table, State Diagram & State Equation.
142) Mealy and Moore State Machines (Part 1).
143) Mealy and Moore State Machines (Part 2).
144) Analysis of Clocked Sequential Circuits (with D Flip Flop).
145) Analysis of Clocked Sequential Circuits (with JK Flip Flop).
146) Analysis of Clocked Sequential Circuits (with T Flip Flop).
147) Behavior of Master Slave D Flip Flop.
148) Sequence or Pattern Detector.
149) Sequence Detector Example.
150) State Reduction and State Assignment.
151) ASM Chart.
152) Design Procedure for Clocked Sequential Circuits.
153) Types of Counters | Comparison between Ripple & Synchronous Counter.
154) 3 Bit Asynchronous Up Counter.
155) 4 Bit Asynchronous Up Counter.
156) State Diagram of a Counter.
157) 3 Bit & 4 Bit Asynchronous Down Counter.
158) 3 Bit & 4 Bit Up/Down Ripple Counter.
159) Modulus of the Counter & Counting up to particular Value.
160) Decade (BCD) Ripple Counter.
161) How to Design Synchronous Counters | 2-Bit Synchronous Up Counter.
162) 3-Bit Synchronous Up Counter.
163) 3 Bit & 4 Bit Up/Down Synchronous Counter.
164) Ring Counter.
165) Johnson's Counter (Twisted/Switch Tail Ring Counter).



























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